Scientech110 Universal Development Platform for FPGAs, CPLDs, CPLDs Cool Runner de Xilinx, etc.

Scientech110

SCIENTECH TECHNOLOGIES

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Scientech TechBooks are compact and user-friendly learning platforms to provide a modern, portable, comprehensive and practical way to learn Technology. Each TechBook is provided with detailed Multimedia learning material which covers smart manual with language tutorial, examples, labs, sample codes in Verilog/VHDL, basic theory, step by step procedure to conduct the experiment and other useful information.

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Category FPGA

Scientech 110 Universal Development Platform has been designed to provide a quick and easy way of learning VLSI front and & embedded design. It is based on mother board -daughter card concept for VLSI designs targeting the FPGAs, CPLDs, Cool runner CPLDs from Xilinx & can also be used in embedded lobs by using ARM7 daughter card. The Development platform contains on board input-output, ADC, DAC, Displays, keyboard & peripheral, which can be used to learn & implement basic as well as advanced VLSI designs.
Scientech 110, Universal Development Platform is an ideal platform to enhance education, training, skills & development among our young minds.

Mother Board Specifications:
- On board : +5V, 3.3V, 2.5V,1.8V supply
LCD display : 16 X 2 Character LCD
7 Segment : 4 digits
8 Channel ADC : 8-bit Resolution
Push button : 4
Output LEDs : 16
DIP switches : 16
HEX keypad : 1
DAC : 8-bit Resolution
Memory : SRAM 32KB
Peripheral Interface : Serial, PS2, VGA, USB etc. Free I/O’s for
Arm 7 daughter card
FPGA Daughter Card
- Xilinx Family : Spartan 3, XC3S400PQ208
- Device density : 400k gates
- On board : 8 MHZ crystal
- Master reset Key : For hardware reset
- On board : EPROM for FPGA boot.
- Configuration Method : JTAG / Boundary scan interface
: PROM interface
CPLD Daughter Card
- Xilinx Family : CPLD, XC95108TQ100
- Device density : 2400 gates, 108 macro cells
- On board : 8 MHZ crystal
- Configuration Method : JTAG interface (boundary scan)
Cool Runner CPLD Daughter Card: (Optional)
Xilinx Family :
- Cool Runner : XCR3128
- Package : VQ100
Device Density :
- 28 macrocells
Configuration Methods :
- IEEE 1149 JTAG Interface (Boundary Scan)
Spartan3E FPGA Daughter Card: (Optional)
- Xilinx Family : Spartan 3E, XC3S500EPQ208
- Device density : 500k gates
- On board : 8 MHZ crystal
- Master reset Key : For hardware reset
- On board : EPROM for FPGA boot.
- Configuration Method : JTAG /Boundary scan interface,
: PROM interface
Spartan3A FPGA Daughter Card: (Optional)
- Xilinx Family : Spartan 3A, XC3S50-ATQFP144
- Device density : 50k gates/1584 logic cells
- On board : EPROM for FPGA boot.
- Configuration Method : JTAG /Boundary scan interface,
: PROM interface
-Spartan6 FPGA Daughter Card: (Optional)
- Xilinx Family : Spartan 6, XC6SLX9 TQ144
- Device density : 9152 logic cells
- On board : EPROM for FPGA boot.
- Configuration Method : JTAG /Boundary scan interface,
: PROM interface
ARM7 Daughter Card: (Optional)
Device Family :
- Philips Semiconductor : LPC2292/94
- Package : LQFP144
Device Density :
- 16/32-bit ARM microcontroller
- 256 KB flash memory
Configuration Methods :
- JTAG Interface
- RS232 Interface
Altera Cyclone II FPGA Daughter Card (Optional)
- Device - EP2C8Q208C8
- Family - Cyclone II
- Number of logic elements/cells -8250
- Number of free dedicated input -5
- Number of clocks-2
- USB Blaster configuration Cable quartus -II web adition
- Peripheral Card :
- RS232(serial port)
- VGA port
- PS2 port
- USB port (Serial to USB)
Digital Boolean Logics, Multiplexers, De-multiplexers
Encoders, Decoder, Priority encoder, Code converter, Parity
generator, Latches & Flip-flop, Shift Registers, BCD Counter,
Address Decoders, ALU, MAC, Interface of 16X2 LCD display,
Interface of HEX keypad, IP Core design of Serial Port, PS2,
VGA, ADC, DAC, SRAM etc.
Included Accessories
- FPGA /CPLD JTAG Cable : 1 No.
- Xilinx USB JTAG Cable (Optional) : 1No.
- Male to Female serial cable : 1 No.
- USB Cable : 1 No.
- Power Supply +12 V : 1 No.
- Xilinx ise Webpack

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